1. Technical Field
The present invention relates to high density, multi-metal layer semiconductor devices with reliable interconnection patterns. The invention has particular applicability in manufacturing ultra large scale integration multi-metal layer semiconductor devices with design features of 0.25 microns and under.
2. Background Art
The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as 0.18 microns, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer is then applied to the resulting conductive pattern to fill in the gaps and the surface is planarized, as by conventional etching or chemical-mechanical polishing (CMP) planarization techniques.
FIGS. 1A, 1B, and 1C illustrate prior art techniques for filling a gap between metal lines. As shown in FIG. 1A, conventional practices comprise depositing metal layer 12 on dielectric layer 10 which is typically formed on a semiconductor substrate containing an active region with transistors (not shown). After photolithography, etching is then conducted to form a patterned metal layer comprising metal lines 12a, 12b with gaps therebetween.
Filling of the gap between metal lines 12a and 12b must be performed without formation of a void, i.e., a location where a deposited oxide layer covers the metal lines 12 but does not completely fill the gap between lines 12a and 12b. A deposited oxide layer that does not completely fill the gap between lines 12a and 12b is also referred to as a "breadloaf" structure. One technique for filling the gap between metal lines 12a and 12b uses spin on glass (SOG) as a gap fill. A thin TEOS adhesion promoting liner 14 is first deposited overlying the metal lines 12a and 12b and the exposed dielectric layer 10 in the gap. A dielectric material 16, such as spin on glass (SOG), is then deposited overlying the TEOS liner 14 to fill in the gaps between the metal lines 12a and 12b. The deposited SOG 16 is baked at a temperature of about 300.degree. C. to about 350.degree. C. , and then cured at about 350.degree. C. to about 400.degree. C. for a period of time up to about one hour, depending upon the particular SOG material employed, to effect planarization. Another oxide layer 18 (e.g., TEOS) is then deposited by plasma enhanced chemical vapor deposition (PECVD) and then planarized by chemical-mechanical polishing (CMP).
FIG. 1B is a side view of the metal line 12a for illustrating formation of a through-hole (i.e., a via). As shown in FIG. 1B, a through-hole 20 is formed in the dielectric layer 18 to expose an underlying feature (e.g., the top surface of metal line 12a), wherein the metal feature 12a serves as a landing pad occupying the entire bottom of the through-hole 20. Outgassing is prevented so long as the top surface of the SOG layer 16 is below the top surface of metal feature 12a, and so long as the metal feature 12a completely encloses the bottom surface of the through-hole 20. A metal plug 30, for example tungsten, is then deposited to form a conductive via between the metal layer 12a and another overlying metal layer 36.
FIG. 1C illustrates an alternative approach for filling the gap between the metal lines 12a and 12b, wherein high density plasma (HDP) oxide is deposited and etched. Specifically, the HDP oxide layer 24 is formed by repeatedly performing deposit and etch steps, which removes any corners that may be formed in a breadloaf pattern in the deposited oxide. Hence, the gap between the metal lines 12a and 12b can be filled without a void and without the necessity of the SOG layer 16 of FIG. 1A. However, the repeated depositing and etching to form the HDP oxide layer 24 has a very slow throughput due to the overall slow rate of deposition. Once the gap between the metal lines 12 has been filled and void formation has been prevented, a layer of TEOS may then be deposited to complete formation of the interlayer dielectric between metal layers.
The reduction of design features to the range of 0.25 microns and under requires extremely high densification. The conventional practice of forming a landing pad completely enclosing the bottom surface of a conductive via utilizes a significant amount of precious real estate on a semiconductor chip which is antithetic to escalating high density requirements. In addition, it is extremely difficult to etch and fill through-holes having such reduced dimensions because of the extremely high aspect ratio, i.e., height of the thorough-hole with respect to diameter of the through-hole. Accordingly, conventional techniques include purposely widening the diameter of the through-hole to decrease the aspect ratio. As a result, normal and unpreventable amounts of misalignment cause the bottom surface of the conductive via to not be completely closed by the underlying metal feature. This type of via is called a "borderless via," and it conserves chip real estate.
The use of borderless vias, however, creates new problems. For example, if misalignment occurs during formation of a via in the arrangement of FIG. 1A, the SOG gap filling layer 16 is penetrated during etching when forming a misaligned through-hole. As a result of such penetration, moisture and gas accumulate during through-hole fill due to the low density and poor stability of SOG, thereby increasing the resistance of the interconnection.
Hydrogen silsesquioxane (HSQ) offers many advantages for use in interconnect patterns. HSQ is relatively carbon free, hence it is not necessary to etch back HSQ below the upper surface of the metal lines to avoid shorting. In addition, HSQ exhibits excellent planarity and is capable of gap filling interwiring spacings less than 0.15 microns employing conventional spin-on equipment. HSQ undergoes a melting phase at approximately 200.degree. C. , but does not convert to the high dielectric constant glass phase until reaching temperatures of about 400.degree. C. for intermetal applications and about 700.degree. C. to about 800.degree. C. for premetal applications. HSQ also is similar to SOG, except that it has a low dielectric constant (low-K) such that it reduces interconnect capacitance and therefore increases circuit speed.
However, HSQ is susceptible to degradation during processing leading to various problems, such as voids (a/k/a "via poisoning") when forming borderless vias. For example, when forming a borderless via, a photoresist mask is deposited and a misaligned through-hole etched to expose a portion of an upper surface and a portion of a side surface of an underlying metal line, and to penetrate into and expose the HSQ layer. Etching to form the through-hole is typically conducted employing reactive ion etching with fluorocarbon chemistry, e.g., CF.sub.4, with an attendant polymer formation. The photoresist mask is then stripped, typically employing an oxygen (O.sub.2)-containing plasma. After the photoresist mask is plasma stripped, the through-hole is conventionally cleaned by employing a wet solvent, to remove polymers formed during reactive ion etching. Solvents conventionally employed include ACT935.TM. and ACT970.TM. available from Ashland Chemical Company in Pennsylvania. A further plasma stripping step is conventionally conducted after wet solvent cleaning.
During experimentation assessing the feasibility of employing HSQ for gap filling in interconnection patterns comprising a borderless via, it was found that the HSQ gap fill layer absorbs water during solvent cleaning of the misaligned through-hole. It was further found that upon subsequent filling of the through-hole, as with a barrier material such as titanium nitride or titanium-titanium nitride, followed by tungsten deposition to fill the via, outgassing occurs whereby voids are generated not only in the portion of the borderless via along a side surface of the lower feature, but throughout the borderless via. Such outgassing was also found to inhibit barrier metal adhesion resulting in undesirable interaction between tungsten hexafluoride, employed to deposit the tungsten, and the aluminum or aluminum alloy primary conductive layer of the lower metal feature.
One proposal to minimize the HSQ outgassing described in commonly-assigned, copending application Ser. No. 08/993,052, filed Dec. 18, 1997, "VACUUM BAKED HSQ GAP FILL LAYER FOR HIGH INTEGRITY BORDERLESS VIAS," (Attorney Docket 50100-428), includes preparing the exposed HSQ prior to filling the borderless via. Specifically, a high-temperature bake was performed, followed by a degas operation. Following the degas operation, the barrier layer (e.g., a TiN liner) was deposited which served as an adhesion promoter for the tungsten plug, and then the tungsten was deposited over the barrier layer to fill the via.
The proposal described in the above-identified application is effective, however, only if the TiN liner serving as a barrier layer completely covers, and thus prevents contact between the exposed HSQ layer surfaces and the tungsten. Outgassing may also occur following TiN liner deposition if poor adhesion is encountered between the deposited TiN liner and the exposed HSQ layer surfaces. Complete coverage of the HSQ layer with the TiN liner may be particularly difficult in a borderless via. For example, the metal layer at one edge of a borderless via is not always a precise angle. Specifically, the metal layer at the edge of a borderless via is coated with an anti-reflective coating, for example a thin layer of Ti (100.ANG.) covered with a 1000.ANG. layer of TiN. When the anti-reflective coating is etched back, a reentrant structure may be formed underneath the edge of the anti-reflective coating, also referred to as an "overhang." If a barrier deposition is attempted, the barrier layer not only needs to cover the sides of the borderless via, but also underneath the vertical overhang. Hence, the structure in a borderless via may prevent complete coating using a TiN barrier deposition before tungsten deposition. Hence, it may be particularly difficult to completely cover using physical vapor deposition.
Outgassing may also occur in bordered vias if HSQ is used to form the structure of FIG. 1B. Specifically, if HSQ is used as a gap fill that fills above the top surface of the metal lines 12, incomplete removal of the deposited HSQ layer from the top of the metal layer may result in residual HSQ between the metal and the dielectric (e.g., TEOS) layer 18). The residual HSQ may thus cause outgassing during formation of the tungsten plug filling the via.
In view of the manifest advantages of HSQ, there exists a need to provide technology whereby HSQ can be employed for voidless gap filling in forming interconnection patterns containing substantially voidless, high integrity borderless vias.
Hence, there is a need for overcoming the adverse effects of outgassing when HSQ is used during the formation or bordered and borderless vias.